Supported features

Kmila implements a VHDL simulator written from scratch in .NET 9. This page summarizes which language constructs the engine recognizes, which widgets the visual runtime offers, and how it estimates FPGA resource usage. The goal is to describe what is documented in the code, without overselling: Kmila solidly covers the constructs most used in digital-design courses and labs.

VHDL constructs

Design units and declarations

The parser recognizes the top-level structures entity, architecture, package, package body and configuration, and the declarations signal, constant, variable, attribute, alias, component, type and subtype. Ports and generics support vector types, ranges and default values.

Custom types

Beyond the standard types, you can define your own: enumerations, arrays (array with index constraints), records (record with fields) and subtypes with constraints. The type registry feeds variable synthesis, operation evaluation, function execution and resource estimation.

Sequential and concurrent statements

Category	Constructs
Sequential control	if / elsif / else, case / when, for-loop, while-loop, simple loop, exit, next, null, return
Concurrent	Signal assignments, conditional when…else, selected with…select, component instantiation with port map / generic map
Generate	for-generate, if-generate and nested generates with local declarations
Blocks	block statements with guard expressions and local declarations; labeled constructs
Subprograms	Functions and procedures with parameters, local variables and sequential-statement bodies
Timing / verification	after clause with time units, wait for, report, assert

Data types

std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, bit, bit_vector, boolean, boolean_vector, integer, integer_vector, natural, positive, signed, unsigned, character, string, time and real.

Operators and expressions

• Arithmetic: +, -, *, /, mod, **
• Logical and shift: and, or, xor, nand, nor, xnor, not, sll, srl, sla, sra, rol, ror
• Relational: =, /=, <, >, <=, >=
• Others: concatenation &, aggregates such as (others => '0'), indexed access to vectors and slices, and function calls inside range expressions (e.g. clog2(N)).

Attributes

During simulation the engine tracks 'event, 'last_value, 'stable and 'active. The parser also recognizes vector attributes such as 'length, 'range, 'high, 'low, 'left, 'right, 'quiet and 'transaction, and the edge detectors rising_edge / falling_edge.

IEEE libraries

A dedicated library compiler resolves use IEEE.* clauses and provides the standard functions from std_logic_1164, numeric_std and math_real (conversions, resize, shifts, math functions), so you don't need to declare them by hand.

The simulation engine is verified systematically against GHDL. See the benchmark for coverage and results.

Visual runtime

Beyond waveforms, Kmila includes a virtual hardware canvas where you bind your design's ports to interactive components: press a button and watch an LED light up, instead of reading waves after the fact. The runtime offers twelve widgets:

LED, Button, Switch, Multi-Switch (2- to 8-lever DIP), LED array, 3×3 LED matrix (monochrome), 3×3 RGB matrix, 7-segment display, Buzzer / Piezo (via Web Audio), matrix keypad, HD44780 LCD (2×16 / 4×20, 4-bit / 8-bit / text modes) and a 4-phase stepper motor.

The canvas opens as an editor tab — Code · Blocks · Step replay · Visual — or by direct URL, and can be exported to SVG, PNG and PDF, as well as recorded to video.

FPGA resource estimation

Even though Kmila needs no hardware, it does tell you how much a design would occupy on a real FPGA. After synthesis, an estimator analyzes each entity and reports:

Resource	How it is estimated	Documented accuracy
Flip-flops	Counts signals assigned in clocked processes (rising_edge / falling_edge)	~95%
LUTs	From the combinational logic	~60–80% (synthesis-dependent)
DSP, BRAM, I/O, clock domains	Per-entity analysis	Estimate

You can pick a target device from 34 bundled FPGA profiles, covering AMD/Xilinx Spartan-6 and Artix-7, Intel/Altera Cyclone IV E, and Lattice iCE40 HX / iCE40 UltraPlus / ECP5. A chip in the editor's status bar goes from green to amber to red as the design grows relative to the selected device.

Next steps

• Understand the execution model in How simulation works.
• Review the terminology in the Glossary.
• Compare Kmila with other tools in Comparison.