Glossary

Short, self-contained definitions of the VHDL and simulation terms that appear in Kmila and its documentation. Each term is meant to be read on its own.

Entity

The interface of a hardware component in VHDL. It declares the block's name, its ports (in, out, inout) and its generic parameters, but not its internal behavior. It is the "contract" other designs use to instantiate it.

Architecture

The implementation of an entity: it describes how the block behaves or is built internally. A single entity can have several architectures (for example, one behavioral and one structural).

Process

A block of sequential statements that runs as a concurrent unit inside an architecture. It re-activates when a signal in its sensitivity list changes, and it is where sequential and combinational logic are described.

Signal

An object that models a wire or a register and carries values over time. It is assigned with <= and its new value is applied in a deferred way, at the end of the delta cycle, not immediately.

Variable

An object local to a process or subprogram, assigned with := and updated immediately. It serves as temporary computation storage, not as a physical wire.

Delta cycle

An infinitesimal simulation step that consumes no simulated time. It resolves, deterministically, several signal changes that happen "at the same instant": all processes are evaluated, then all signal updates are applied at once.

Elaboration

The stage that turns the syntax tree into a runnable model: it resolves entities, architectures, components, packages and IEEE libraries, and fixes the real width of every signal and vector.

Sensitivity list

The set of signals a process "watches." The process re-runs only when one of them changes. For combinational logic it must include every input read; for sequential logic it usually includes only the clock (and the asynchronous reset).

'event attribute

A signal attribute that is true when the signal has just changed value in the current delta cycle. It is the basis of edge detection: rising_edge(clk) is equivalent to clk'event and clk = '1'.

'stable attribute

An attribute that is true when a signal has not changed over a given interval; it is essentially the complement of 'event. Kmila also tracks 'last_value (the previous value) and 'active.

std_logic

The standard data type (from the IEEE.std_logic_1164 library) for a single bit of digital logic. It admits nine values, not just '0' and '1': for example 'Z' (high impedance), 'X' (unknown) and 'U' (uninitialized).

std_logic_vector

An array of std_logic values representing a multi-bit bus, for example std_logic_vector(7 downto 0) for an 8-bit bus. The related types signed and unsigned (from IEEE.numeric_std) add arithmetic interpretation.

VCD (Value Change Dump)

A standard file format that records every value change of the signals over time. Kmila exports GTKWave-compatible VCD, as well as CSV and text.

Netlist

A structural description of a circuit as a graph of cells (gates, registers) connected by nets. Kmila generates it in a synthesis pass, independent of the simulation, to draw the schematic view.

Testbench

A VHDL design whose only job is to stimulate and verify another design (the DUT): it generates clocks and inputs, and checks the outputs. It does not represent synthesizable hardware.

RTL (Register-Transfer Level)

A style of describing hardware in terms of registers and the data transfers between them on each clock edge. It is the usual abstraction level for writing synthesizable digital designs.

Synthesis

The process of translating a behavioral (RTL) description into a structural implementation in terms of hardware primitives. Kmila performs a netlist synthesis for visualization and resource estimation; it does not generate a bitstream for a physical FPGA.

FPGA (Field-Programmable Gate Array)

A reconfigurable chip whose logic is programmed after manufacturing. Kmila lets you learn and debug designs without an FPGA, by simulating them in software, and estimates how many resources they would use on a target device.

LUT (Look-Up Table)

The basic block an FPGA uses to implement combinational logic: a small table that produces an output for each combination of inputs. Kmila estimates a design's LUT usage.

Flip-flop

The clock-synchronized one-bit storage element; registers are built from flip-flops. Kmila estimates the number of flip-flops by counting the signals assigned inside clocked processes.