KmilaAnatomy of a VHDL file
library, use, entity, architecture — what each section is for and why it's in that order.
VHDL basics
The anatomy of a VHDL file, types you'll actually use, and how signals differ from variables.
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Data types: std_logic, vectors, unsigned, integer
Which type to use when — and why std_logic has nine values, not two.
Signal vs. variable
The single most misunderstood distinction in VHDL, illustrated with a delta-cycle trace.
Sample: your first entity (2-to-1 MUX)
Open a tiny 2-to-1 multiplexer and watch the output track the selected input.