How VHDL simulation works

Kmila is a real VHDL simulator, written from scratch in .NET 9. It does not hand your design off to another tool and it does not depend on an FPGA: it interprets the language and reproduces, tick by tick, how a digital circuit's signals would behave over time. This page explains the execution model behind the Run button.

The engine's four stages

From text to waveform, a design passes through four stages. Each takes the output of the previous one and refines it into a runnable model.

flowchart LR
    A["1. Parsing<br/>(analysis)"] --> B["2. Elaboration"]
    B --> C["3. Simulation<br/>(delta cycles)"]
    C --> D["4. Output<br/>(VCD / CSV / waves)"]

1. Parsing (analysis)

The tokenizer reads the VHDL, strips comments and classifies every element (keywords, identifiers, operators, literals). The parser validates that sequence against the VHDL grammar and builds an abstract syntax tree (AST): entities, architectures, packages, processes and statements become in-memory objects. If the code has an error, it is reported here with line, column and context.

2. Elaboration

The AST is not yet runnable. Elaboration resolves entities and architectures, instantiates components (port map / generic map), links packages and the IEEE libraries (std_logic_1164, numeric_std, math_real) and computes the real width of every signal and vector. The result is a hierarchical model the scheduler can walk.

3. Simulation (delta cycles)

This is the heart of the engine: an event-driven scheduler that advances time in discrete ticks and, within each instant of time, in delta cycles. The sections below go into detail.

4. Output

Every signal transition is recorded in a history (SignalHistory) that becomes interactive waveforms and is exported to VCD (GTKWave-compatible), CSV or text. In parallel, an independent synthesis pass can lower the behavior into a structural netlist for the schematic view.

Event-driven simulation

A circuit does not run line by line like an imperative program. VHDL describes hardware that reacts to events: when a signal changes value, the processes that watch it are re-evaluated. Kmila implements exactly that model.

• Time advances in discrete ticks. The time source (TimeMachine) defines a resolution of 10 ns per tick (NS_PER_TICK = 10).
• Clocks are modeled as signals that toggle their state according to their frequency (in MHz) as the ticks advance.
• A process is only re-activated when a signal in its sensitivity list changes.

Delta cycles: time within time

The subtlest point of VHDL simulation is that several signals can change "at the same time." To resolve this deterministically, VHDL introduces the delta cycle: an infinitesimal step that consumes no simulated time.

Kmila's scheduler uses a two-phase approach within each instant:

1. Evaluation. All active processes compute their assignments, but the new values are not applied yet; they are scheduled.
2. Update. All scheduled values are applied at once. If any signal changed, the processes sensitive to it are marked for another delta cycle.

These delta cycles repeat until no value changes (the circuit settles); only then does the clock advance to the next tick. A combinational loop that never settles is stopped by a maximum delta-cycle cap, which keeps the simulation from hanging.

Signals versus variables

This distinction is the foundation of a design behaving correctly:

Aspect	Signal (signal)	Variable (variable)
Update	Deferred: at the end of the delta cycle	Immediate: as soon as the assignment runs
Operator	<=	:=
Scope	Architecture or process	Only inside a process/subprogram
Models	Wires and registers	Temporary computation storage

The fact that signals update in a deferred way is exactly what makes the delta-cycle model possible and what lets you describe registers with rising_edge(clk).

Signal attributes

During simulation, Kmila tracks the attributes that depend on each signal's history: 'event (did it change in this delta?), 'last_value (previous value), 'stable and 'active. The edge detectors rising_edge and falling_edge are built on 'event — the idiomatic way to describe synchronous sequential logic.

From simulation to waveform

Everything that happens during simulation is stored as a sequence of (tick, signal, value) transitions. That history feeds:

• Interactive waveforms, with bit-expandable buses and a value cursor.
• Export to VCD, which you can open in GTKWave, or to CSV for external analysis.
• The visual runtime, where ports bind to LEDs, buttons and displays.

Because the engine implements the real VHDL model, its results can be checked against a reference simulator. Kmila does this systematically: see the benchmark methodology for how it is compared case by case against GHDL.

Next steps

• Review the terminology in the Glossary.
• See which VHDL constructs the engine supports in Supported features.
• Go deeper in the IEEE / synthesis pipeline and the Architecture.