Engine validated against GHDL · 148/148

Learn and debug VHDL without touching an FPGA.

A unified environment to edit, simulate and visualize digital design. Free, open-source, and on any device.

Try the demo → See the simulator

// 0 installs · 0 licenses · 0 hardware required

counter.vhdl

1entity counter is

2 port(clk, rst : in std_logic;

3 q : out std_logic_vector(3 downto 0));

4end counter;

6architecture rtl of counter is

7 signal cnt : unsigned(3 downto 0);

8begin

9 process(clk) begin

10 if rising_edge(clk) then cnt <= cnt + 1;

11 end if;

12 end process; q <= std_logic_vector(cnt);

What is Kmila?t = 0 → 120 ns

148/148cases identical to GHDL

6target platforms

7languages

34FPGA profiles

// Who it's for

Built for people learning and teaching digital design.

Students

Practice VHDL for your courses and labs without buying an FPGA or installing anything.

Self-learners

Learn digital design at your own pace, with interactive lessons and auto-graded challenges.

Educators & universities

Bring a full HDL lab to your classroom: zero install for 30 students, on any device.

Open-source community

An auditable VHDL simulator written from scratch in .NET and verified against GHDL. MIT-licensed, public soon.

// The complete environment

A whole HDL lab, in a single app.

GHDL, GTKWave and an editor — brought together, with nothing to configure. Kmila integrates the entire digital-design flow.

Smart VHDL editor

Editor with highlighting, inline diagnostics and a bidirectional VHDL ↔ blocks editor.

A real simulation engine

Delta cycles, signal attributes and schedulers. VCD output equivalent to GHDL, verified case by case.

Interactive waveforms

Viewer with zoom, per-bit expandable buses, a value cursor, and export to VCD / SVG / PNG.

Visual runtime

Wire LEDs, buttons, switches and 7-segment displays to your design and watch it run like a breadboard.

Live debugging

Breakpoints by signal and by condition, step-by-step execution and active-line highlighting on the schematic.

FPGA resource estimation

Synthesis to a netlist with a schematic view and approximate resource estimates for 34 FPGA models.

// In action

See it in action — on your desktop and in your pocket.

Real screenshots of Kmila running on desktop, web and mobile.

VHDL editor with autocomplete and live validation.

// From idea to waveform

Three steps. Zero friction.

Write

Open an example or create a project. Write VHDL in the editor — or drag it out with blocks.

Simulate

Hit Run. The engine elaborates your design, resolves the delta cycles and captures every transition.

Visualize

Explore the waveforms, the schematic and the visual runtime. Debug, tweak, repeat.

// Run it your way

Native, web and container.

One codebase on .NET 9. Install it, open it in the browser, or spin it up with Docker on your Linux server.

Windows MAUI

macOS MAUI

Linux Web · Docker

Android MAUI

iOS MAUI

// Open source · Made at ESCOM–IPN

Start simulating in under a minute.

No paid accounts, no hardware, no toolchains. Just your design and a waveform.

Try the demo in the browser → Download the app

Open source (MIT). The repository will be public soon.