Learn VHDL
.From your very first bit to a pipelined CPU — guided readings, worked samples, fix-the-bug exercises, and full projects. Track your progress and open anything straight into the Kmila editor.
Continue where you left off Number systems: bits, hex, two's complementDigital FundamentalsStart from zero
Binary, boolean algebra, gates — the mental model you need before you write a single line of VHDL.
Your first VHDL
VHDL syntax, combinational design, simulation. Short lessons, one concept each.
Bring it to life
Processes, flip-flops, counters, finite-state machines — the moment static circuits start to remember.
Sequential logic
Circuits that remember. Flip-flops, registers, shift registers, counters.
Finite-state machines
Control logic that remembers where it is — Mealy vs Moore, two-process and three-process patterns.
Concurrent thinking
VHDL is not software — every statement outside a process runs at the same time. Master this or fight the tools forever.
Systems that compute
Memories, ALUs, small CPUs, bus protocols. Multi-module designs where pieces talk to each other.
Memories (ROM and RAM)
Infer block RAM and ROM from portable VHDL — no vendor primitives, no macros.
Arithmetic units
From a 4-bit adder to a full 8-bit ALU with flags and a shifter.
Serial communication (UART)
The simplest real-world protocol — start bit, 8 data bits, stop bit, no handshake.
Testbenches and verification
Write a self-checking testbench instead of eyeballing waveforms. The shift from "it looks right" to "it passes".
Graduate-level
Pipelining, hazards, verification, SoC integration. The material from a Sistemas en Chip or Computer Architecture course.
A small CPU
A single-cycle 8-bit RISC datapath — four instructions, no pipelining. All the pieces from earlier, assembled.
Systems-on-Chip
CPUs + peripherals + interconnects. AXI, Avalon, Wishbone — what the protocols actually do.
Pipelining and hazards
From single-cycle to pipelined: data/control/structural hazards and the forwarding logic that papers over them.